/**
 @file sys_usw_port.h

 @author  Copyright (C) 2011 Centec Networks Inc.  All rights reserved.

 @date 2011-11-9

 @version v2.0

*/

#ifndef _SYS_USW_PORT_H
#define _SYS_USW_PORT_H
#ifdef __cplusplus
extern "C" {
#endif

/****************************************************************
 *
 * Header Files
 *
 ***************************************************************/
#include "sal.h"

#include "ctc_const.h"
#include "ctc_vlan.h"
#include "ctc_port.h"
#include "ctc_security.h"
#include "ctc_interrupt.h"
#include "ctc_register.h"

/****************************************************************
*
* Defines and Macros
*
****************************************************************/
#define SYS_USW_MIN_FRAMESIZE_DEFAULT_VALUE    64
#define SYS_USW_ILOOP_MIN_FRAMESIZE_DEFAULT_VALUE    20
#define SYS_USW_MAX_FRAMESIZE_DEFAULT_VALUE    9600u
#define SYS_USW_MAX_FRAMESIZE_TX_INDEX    16
#define SYS_USW_PORT_HAS_EXTRA_CHAN(mode, enable)  ((CTC_XPIPE_MODE_1 == mode && CTC_PORT_XPIPE_TYPE_4 != enable && \
                                                   CTC_PORT_XPIPE_TYPE_5 != enable) ||(CTC_XPIPE_MODE_1 != mode && mode))
#define SYS_USW_MAX_CHANEL_NUM_PER_PORT 3

#define SYS_PORT_MAP_GCHIP_TO_LCHIP(gchip, lchip) \
    do{\
        if (gchip > MCHIP_CAP(SYS_CAP_GCHIP_CHIP_ID) || (gchip == CTC_LINKAGG_CHIPID))\
        {\
            return CTC_E_INVALID_CHIP_ID;\
        }\
        if(!g_ctcs_api_en)\
        {\
            if (CTC_E_NONE != sys_usw_get_local_chip_id(gchip, &lchip))\
            {\
                lchip = 0;\
                do{\
                    if (CTC_E_NONE == sys_usw_chip_check_active(lchip)) {\
                        break; }\
                    lchip++;\
                }while(lchip < g_lchip_num);\
                if (lchip == g_lchip_num){\
                    return CTC_E_INVALID_CHIP_ID; }\
            }\
        }\
    }while(0);

/**
  @brief   Define port property flags
*/
enum sys_port_internal_property_e
{
    SYS_PORT_PROP_DEFAULT_PCP = 0,
    SYS_PORT_PROP_DEFAULT_DEI = 1,
    SYS_PORT_PROP_OAM_TUNNEL_EN = 2,
    SYS_PORT_PROP_OAM_VALID = 3,
    SYS_PORT_PROP_DISCARD_NONE_8023OAM_EN = 5,
    SYS_PORT_PROP_REPLACE_TAG_EN = 6,
    SYS_PORT_PROP_USE_INNER_COS = 7,
    SYS_PORT_PROP_EXCEPTION_EN = 8,
    SYS_PORT_PROP_EXCEPTION_DISCARD = 9,
    SYS_PORT_PROP_SECURITY_EXCP_EN = 10,
    SYS_PORT_PROP_SECURITY_EN = 11,
    SYS_PORT_PROP_MAC_SECURITY_DISCARD = 12,
    SYS_PORT_PROP_QOS_POLICY,
    SYS_PORT_PROP_REPLACE_DSCP_EN,
    SYS_PORT_PROP_STMCTL_EN,
    SYS_PORT_PROP_STMCTL_OFFSET,
    SYS_PORT_PROP_LINK_OAM_EN,
    SYS_PORT_PROP_LINK_OAM_MEP_INDEX,
    SYS_PORT_PROP_SERVICE_POLICER_VALID,
    SYS_PORT_PROP_SPEED_MODE,
    SYS_PORT_PROP_DOT1AE_TX_SCI_EN,
    SYS_PORT_PROP_MAC_AUTH_EN,
    SYS_PORT_PROP_LINK_OAM_LEVEL,
    SYS_PORT_PROP_OAM_MIP_EN,
    SYS_PORT_PROP_INGRESS_POLICER_EN,
    SYS_PORT_PROP_EGRESS_POLICER_EN,
    SYS_PORT_PROP_INGRESS_POLICER_PTR,
    SYS_PORT_PROP_EGRESS_POLICER_PTR,
    SYS_PORT_PROP_INGRESS_POLICER_LEVEL,
    SYS_PORT_PROP_EGRESS_POLICER_LEVEL,
    SYS_PORT_PROP_MICRO_BFD_EN,
    SYS_PORT_PROP_ETH_TO_CPU_ILOOP_EN,
    SYS_PORT_PROP_FLEX_DST_ISOLATEGRP_SEL,
    SYS_PORT_PROP_MUX_PORT_TYPE,
    SYS_PORT_PROP_EVB_LOCAL_PHY_PORT_VALID,
    SYS_PORT_PROP_VLAN_OPERATION_DIS,
    SYS_PORT_PROP_UNTAG_DEF_VLAN_EN,
    SYS_PORT_PROP_STP_EN,
    SYS_PORT_PROP_STP_CHECK_EN,
    SYS_PORT_PROP_DEST_L3IF_ID,
    SYS_PORT_PROP_LOGIC_PORT_TYPE_EN,
    SYS_PORT_PROP_NUM
};
typedef enum sys_port_internal_property_e  sys_port_internal_property_t;

enum sys_port_internal_direction_property_e
{
    SYS_PORT_DIR_PROP_L2_SPAN_EN,
    SYS_PORT_DIR_PROP_L2_SPAN_ID,
    SYS_PORT_DIR_PROP_ETHER_OAM_EDGE_PORT,
    SYS_PORT_DIR_PROP_ETHER_OAM_LOCK_EN,
    SYS_PORT_DIR_PROP_LINK_LM_TYPE,
    SYS_PORT_DIR_PROP_LINK_LM_COS,
    SYS_PORT_DIR_PROP_LINK_LM_COS_TYPE,
    SYS_PORT_DIR_PROP_LINK_LM_INDEX_BASE,
    SYS_PORT_DIR_PROP_LINK_LOCK,
    SYS_PORT_DIR_PROP_ETHER_LM_VALID,
    SYS_PORT_DIR_PROP_MPLS_SECTION_LM_EN,
    SYS_PORT_DIR_PROP_MPLS_SECTION_LOCK_EN,
    SYS_PORT_DIR_PROP_DOT1AE_SA_IDX_BASE,
    SYS_PORT_DIR_PROP_OAM_VALID,
    SYS_PORT_DIR_PROP_NUM
};
typedef enum sys_port_internal_direction_property_e  sys_port_internal_direction_property_t;


enum sys_port_vlan_filter_mode_e
{
    SYS_PORT_VLAN_FILTER_MODE_VLAN,
    SYS_PORT_VLAN_FILTER_MODE_ENABLE,
    SYS_PORT_VLAN_FILTER_MODE_DISABLE,
    SYS_PORT_VLAN_FILTER_MODE_NUM
};
typedef enum sys_port_vlan_filter_mode_e sys_port_vlan_filter_mode_t;


#define SYS_USW_ISOLATION_GROUP_NUM            32
#define SYS_USW_ISOLATION_ID_NUM               64


#define SYS_INVALID_LOCAL_PHY_PORT                    0xFFFF

struct sys_port_prop_s
{
    uint32 lbk_en             :1;
    uint32 subif_en           :1;
    uint32 xfabric_type       :3;/*AT, 0:NONE;1:profile0;2:profile1*/
    uint32 xpipe_type         :3;      /* used for get xpipe type */
    uint32 is_mac_da          :1;
    uint32 ptp_domain_id      :1;
    uint32 rsv                :22;

    uint32 inter_lport        :16;
    uint32 global_src_port    :16;

    uint32 nhid;
};
typedef struct sys_port_prop_s sys_port_prop_t;

struct sys_usw_port_mac_config_s
{
    uint32 speed_value;     /* TMM, in */
    uint16 lport;           /* in */
    uint8  interface_type;  /* TMM, in */
    uint8  speed_mode;      /* in */
    uint8  is_init;         /* in */
};
typedef struct sys_usw_port_mac_config_s sys_usw_port_mac_config_t;

enum sys_port_scl_action_type_e
{
    SYS_PORT_SCL_ACTION_TYPE_SCL,
    SYS_PORT_SCL_ACTION_TYPE_FLOW,
    SYS_PORT_SCL_ACTION_TYPE_TUNNEL,
    SYS_PORT_SCL_ACTION_TYPE_MAX
};
typedef enum sys_port_scl_action_type_e sys_port_scl_action_type_t;

typedef int32 (*SYS_PORT_GET_RCHIP_GPORT_IDX_CB)(uint8 lchip, uint32 gport, uint16* p_glb_port_index);

#define SYS_PORT_TX_MAX_FRAME_SIZE_NUM  16

struct sys_port_master_s
{
    sys_port_prop_t* port_prop;
    uint16*               network_port; /*for wlan store network port with internal port*/
    sal_mutex_t*          p_port_mutex;

    uint32   use_logic_port_check   : 1;
    uint32   use_isolation_id       : 1; /*use_isolation_id == 0 means configure basing port port isolation;
                                           use_isolation_id == 1 means configure basing group port isolation*/
    uint32   isolation_group_mode   : 4;
    uint32   opf_type_port_sflow    : 8;
    uint32   cpu_eth_loop_en        : 1;
    uint32   rsv                    : 17;
    uint32   igs_isloation_bitmap[2];
    SYS_PORT_GET_RCHIP_GPORT_IDX_CB rchip_gport_idx_cb; /*this callback function is used for get global dest port index*/
    uint8   tx_frame_ref_cnt[SYS_PORT_TX_MAX_FRAME_SIZE_NUM];      /* Share pool save tx max frmae size and min frame size */
    uint32  reflect_en[16];
    uint16  internal_port_start;
};
typedef struct sys_port_master_s sys_port_master_t;

struct sys_scl_type_para_s
{
    uint8 tunnel_en        :1;
    uint8 auto_tunnel      :1;
    uint8 nvgre_en         :1;
    uint8 vxlan_en         :1;
    uint8 tunnel_rpf_check :1;
    uint8 use_macda        :1;
    uint8 tcam_en          :1;
    uint8 vlan_high_priority              :1;
    uint8 drv_hash_type;
    uint8 ctc_hash_type;
    uint8 drv_tcam_type;
    uint8 ctc_tcam_type;
};
typedef struct sys_scl_type_para_s sys_scl_type_para_t;

extern sys_port_master_t* p_usw_port_master[CTC_MAX_LOCAL_CHIP_NUM_PP];

#define SYS_PORT_DBG_OUT(level, FMT, ...) \
    do { \
        CTC_DEBUG_OUT(port, port, PORT_SYS, level, FMT, ##__VA_ARGS__); \
    } while (0)


/****************************************************************************
 *
* Function
*
*****************************************************************************/
extern int32
sys_usw_port_init(uint8 lchip, ctc_port_global_cfg_t* p_port_global_cfg);

extern int32
sys_usw_port_deinit(uint8 lchip);

extern int32
sys_usw_port_set_default_cfg(uint8 lchip, uint32 gport);

/*external property*/
extern int32
sys_usw_port_set_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value);

extern int32
sys_usw_port_mac_config_attach(uint8 lchip, sys_usw_port_mac_config_t* port_mac_config);

extern int32
sys_usw_port_get_property(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32* p_value);

extern int32
sys_usw_port_set_restriction(uint8 lchip, uint32 gport, ctc_port_restriction_t* p_restriction);

extern int32
sys_usw_port_get_restriction(uint8 lchip, uint32 gport, ctc_port_restriction_t* p_restriction);

extern int32
sys_usw_port_set_isolation_mode(uint8 lchip, uint8 choice_mode);

extern int32
sys_usw_port_get_isolation_mode(uint8 lchip, uint8* p_choice_mode);

extern int32
sys_usw_port_set_isolation(uint8 lchip, ctc_port_isolation_t* p_restriction);

extern int32
sys_usw_port_get_isolation(uint8 lchip, ctc_port_isolation_t* p_restriction);

extern int32
sys_usw_port_set_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32 value);

extern int32
sys_usw_port_get_direction_property(uint8 lchip, uint32 gport, ctc_port_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value);
/*internal property*/

extern int32
sys_usw_port_set_internal_property(uint8 lchip, uint32 gport, sys_port_internal_property_t port_prop, uint32 value);

extern int32
sys_usw_port_get_internal_property(uint8 lchip, uint32 gport, sys_port_internal_property_t port_prop, uint32* p_value);

extern int32
sys_usw_port_set_internal_direction_property(uint8 lchip, uint32 gport, sys_port_internal_direction_property_t port_prop, ctc_direction_t dir, uint32 value);

extern int32
sys_usw_port_get_internal_direction_property(uint8 lchip, uint32 gport, sys_port_internal_direction_property_t port_prop, ctc_direction_t dir, uint32* p_value);

extern int32
sys_usw_port_set_port_mac(uint8 lchip, uint32 gport, mac_addr_t mac_da);
extern int32
sys_usw_port_update_mc_linkagg(uint8 lchip, uint16 tid, uint16 lport, bool is_add);

extern int32
sys_usw_port_set_global_port(uint8 lchip, uint16 lport, uint32 gl_port, bool update_mc_linkagg);

extern int32
sys_usw_port_get_global_port(uint8 lchip, uint16 lport, uint32* p_gl_port);

extern int32
sys_usw_port_set_phy_if_en(uint8 lchip, uint32 gport, bool enable);

extern int32
sys_usw_port_get_phy_if_en(uint8 lchip, uint32 gport, uint16* p_l3if_id, bool* p_enable);

extern int32
sys_usw_port_set_sub_if_en(uint8 lchip, uint32 gport, bool enable);

extern int32
sys_usw_port_get_sub_if_en(uint8 lchip, uint32 gport, bool* p_enable);

extern int32
sys_usw_port_set_scl_key_type(uint8 lchip, uint32 gport, ctc_direction_t direction, uint8 sal_id, ctc_port_scl_key_type_t type);

extern int32
sys_usw_port_get_scl_key_type(uint8 lchip, uint32 gport, ctc_direction_t direction, uint8 sal_id, ctc_port_scl_key_type_t* p_type);

extern int32
sys_usw_port_set_vlan_range(uint8 lchip, uint32 gport, ctc_vlan_range_info_t* p_vrange_info, bool is_svlan, bool enable);

extern int32
sys_usw_port_get_vlan_range(uint8 lchip, uint32 gport, ctc_vlan_range_info_t* p_vrange_info, bool* p_enable);

extern int32
sys_usw_port_set_loopback(uint8 lchip, ctc_port_lbk_param_t* p_port_lbk);

extern int32
sys_usw_port_set_ipg_size(uint8 lchip, ctc_ipg_size_t index, uint8 size);

extern int32
sys_usw_port_get_ipg_size(uint8 lchip, ctc_ipg_size_t index, uint8* p_size);

extern int32
sys_usw_port_set_port_mac_prefix(uint8 lchip, ctc_port_mac_prefix_t* p_port_mac);

extern int32
sys_usw_port_set_port_mac_postfix(uint8 lchip, uint32 gport, ctc_port_mac_postfix_t* p_port_mac);

extern int32
sys_usw_port_get_port_mac(uint8 lchip, uint32 gport, mac_addr_t* p_port_mac);

extern int32
sys_usw_port_set_port_cross_connect(uint8 lchip, uint32 gport, uint32 nhid);

extern int32
sys_usw_port_get_port_cross_connect(uint8 lchip, uint32 gport, uint32* p_value);

/* ipg is mac tx property. value: 3 is 12Bytes, 2 is 8Bytes, 1 is 4Bytes, default is 12Bytes */
extern int32
sys_usw_port_mac_set_ipg(uint8 lchip, uint32 gport, uint32 value);

extern int32
sys_usw_port_set_scl_property(uint8 lchip, uint32 gport, ctc_port_scl_property_t* p_prop);

extern int32
sys_usw_port_get_scl_property(uint8 lchip, uint32 gport, ctc_port_scl_property_t* p_prop);

extern int32
sys_usw_port_set_acl_property(uint8 lchip,uint32 gport, ctc_acl_property_t* p_prop, uint8 block_num, uint8 *block_list);

extern int32
sys_usw_port_get_acl_property(uint8 lchip,uint32 gport, ctc_acl_property_t* p_prop);

extern int32
sys_usw_port_set_acl_league_property(uint8 lchip, uint8 acl_pri, uint8 enable, uint8 sub_blk_cnt, uint8 *sub_blk_list);

extern int32
sys_usw_port_set_bpe_property(uint8 lchip, uint32 gport, ctc_port_bpe_property_t* p_prop);

extern int32
sys_usw_port_get_bpe_property(uint8 lchip, uint32 gport, ctc_port_bpe_property_t* p_prop);

extern int32
sys_usw_port_get_local_phy_port(uint8 lchip, uint32 gport, uint32* p_value);

extern int32
sys_usw_port_register_rchip_get_gport_idx_cb(uint8 lchip, SYS_PORT_GET_RCHIP_GPORT_IDX_CB cb);

extern int32
sys_usw_port_glb_dest_port_init(uint8 lchip, uint16 glb_port_index);

extern int32
sys_usw_port_set_mac_auth(uint8 lchip, uint32 gport, bool enable);

extern int32
sys_usw_port_get_mac_auth(uint8 lchip, uint32 gport, bool* enable);

extern int32
sys_usw_port_set_flow_ctl_en(uint8 lchip, void* p_fc_prop, uint8 is_recover);

extern int32
sys_usw_port_get_flow_ctl_en(uint8 lchip, void* p_fc_prop);

extern int32
sys_usw_port_set_port_swap(uint8 lchip, uint32 src_gport, uint32 dst_gport);

extern int32
sys_usw_port_wb_sync(uint8 lchip,uint32 app_id);

extern int32
sys_usw_port_wb_restore(uint8 lchip);

extern int32
sys_usw_port_lport_convert(uint8 lchip, uint16 internal_lport, uint16* p_value);

extern int32
_sys_usw_port_map_scl_type(uint8 lchip, uint8 dir, sys_scl_type_para_t* p_scl_type_para);

extern int32
sys_usw_port_set_if_status(uint8 lchip, uint16 lport, uint32 value);

extern int32
sys_usw_port_set_mirror_en(uint8 lchip , uint16 lport, uint8 type, uint32 dsfwd_offset, bool is_add);

extern int32
sys_duet2_set_min_frame_size(uint8 lchip, ctc_frame_size_t index, uint16 value);

extern int32
sys_duet2_get_min_frame_size(uint8 lchip, ctc_frame_size_t index, uint16* p_value);

extern int32
sys_duet2_set_max_frame_size(uint8 lchip, ctc_frame_size_t index, uint16 value);

extern int32
sys_duet2_get_max_frame_size(uint8 lchip, ctc_frame_size_t index, uint16* p_value);
extern int32
sys_usw_port_get_port_reflective(uint8 lchip, uint32* p_bmp);

extern int32
sys_usw_port_set_glb_dest_port_by_dest_port(uint8 lchip, uint16 lport);

extern int32
sys_usw_port_set_scl_hash_tcam_priority(uint8 lchip, uint32 gport, uint8 scl_id, uint8 is_tcam, uint8 value);

extern int32
sys_usw_port_dump_db(uint8 lchip, sal_file_t dump_db_fp,ctc_global_dump_db_t* p_dump_param);

extern int32
sys_usw_port_get_channel(uint8 lchip, uint8 rx, uint32 gport, uint32 *chan, uint8 *chan_num);

extern int32
sys_usw_port_get_mac(uint8 lchip, uint8 rx, uint32 gport, uint32* mac, uint8* mac_num);

extern int32
sys_usw_port_check_xpipe(uint8 lchip, uint32 gport, ctc_port_property_t port_prop, uint32 value);

extern int32
sys_usw_port_set_logic_port_property(uint8 lchip,uint32 logic_port,ctc_logic_port_property_t logic_port_prop,ctc_direction_t dir,void* p_value);

extern int32
sys_usw_port_get_logic_port_property(uint8 lchip,uint32 logic_port,ctc_logic_port_property_t logic_port_prop,ctc_direction_t dir,void* p_value);

#ifdef __cplusplus
}
#endif

#endif

